Nonvolatile semiconductor memory with a page mode

ABSTRACT

A first address subset is allocated as a first column address in a nonvolatile semiconductor memory. In addition, a second address subset higher in order than the first address subset is allocated as a first row address. Furthermore, a third address subset higher in order than the second address subset is allocated as a second column address.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based upon and claims the benefit of priorityfrom the prior Japanese Patent Application No. 2001-269423, filed Sep.5, 2001, the entire contents of which are incorporated herein byreference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] This invention relates to a non-volatile semiconductor memory,such as a flash memory, and more particularly to an address allocatingmethod for a nonvolatile semiconductor memory with a page mode (pagereading function).

[0004] 2. Description of the Related Art

[0005] One known nonvolatile semiconductor memory is a flash memory.FIG. 1 is a sectional view of a memory cell in the flash memory. Thememory cell (or memory cell transistor) is composed of a MOSFET (MetalOxide Semiconductor Field-Effect Transistor), which has a stacked-gatestructure where a floating gate FG and a control gate CG are stacked ontop of the other via an insulating film. Specifically, in this example,an N-well region 101 is formed in a P-substrate. In the N-well region101, a P-well region 102 is formed. At the surface of the P-well region102, an n⁺-type impurity diffused region 103 acting as the drain regionof the MOSFET, an n⁺-type impurity diffused region 104 acting as thesource region, and a p⁺-type impurity diffused region 105 are formed. Onthe substrate 100 between the impurity diffused regions 103 and 104, agate insulating film 106, a floating gate FG, an insulating film 107,and a control gate CG are stacked in that order. At the surface of theN-well region 101, there is provided an n⁺-type impurity diffused region108, which is connected to the impurity diffused region 104 and impuritydiffused region 105. In addition, at the main surface of the substrate100, there is provided a p⁺-type impurity diffused region 109, which isthen connected to the ground point.

[0006] In the memory cell transistor, the threshold voltage with respectto the control gate CG changes (or shifts) according to the number ofelectrons accumulated in the floating gate FG. The memory celltransistor stores “0” or “1” data according to a change in the thresholdvoltage.

[0007]FIG. 2 shows a part of a memory cell array where units of thememory cell transistor are arranged in a matrix. The control gates ofthe individual memory cell transistors MC are connected to word linesWL0 to WLn on a row basis. The drains of the individual memory celltransistors MC are connected to bit lines BL0 to BLm on a column basis.The sources of the individual memory cell transistors MC are allconnected to a ground point Vss (source line).

[0008]FIG. 3 shows the relationship between the control gate voltage andthe drain current in the memory cell transistor of FIG. 1. A state wherethe number of electrons accumulated in the floating gate FG isrelatively large (that is, the threshold voltage Vt of the memory celltransistor is high) is defined as “0” data. Conversely, a state wherethe number of electrons accumulated in the floating gate FG isrelatively small (that is, the threshold voltage Vt of the memory celltransistor is low) is defined as “1” data. The bias conditions for datareading, erasing, and writing are shown in TABLE 1: TABVLE 1 ReadProgram Erase Vg 5 V 9 V −7 V Vd 1 V 5 (“0”) Floating 0 (“1”) Vs 0 V 0 V10 V

[0009] The data is read by applying voltage Vd (=1 V) to the drain ofthe memory cell transistor, voltage Vs (=0 V) to the source, and voltageVg (=5 V) to the control gate CG. Whether the stored data is “1” or “0”is determined, depending on whether cell current Icell flows or not.

[0010] Erasing is effected all at once on the memory cells that sharethe source and the P-well region 102. When the drain is set in thefloating state, the source voltage Vs is set to Vs=10 V, and the controlgate voltage Vg is set to Vg=−7 V, electrons flow from the floating gateFG to the substrate because of an F-N tunnel phenomenon, which sets allof the memory cells to be erased to “1” data.

[0011] In contrast, writing is done bit by bit. In a state where thesource voltage Vs is set to Vs=0 V and the control gate voltage Vg isset to Vg=9 V, a 5 V bias (drain voltage Vd=5 V) is applied to the bitline of the cell into which “0” is to be written, which causeshigh-energy electrons generated in a channel hot electron phenomenon tobe injected into the floating gate. At this time, when the bit line tobe kept at “1” is set to 0 V (drain voltage Vd=0 V), this preventselectrons from being injected, resulting in no change in the thresholdvoltage Vt.

[0012] Next, to check the program or erase operation, program verify orerase verify is performed. In the program verify, the control gatevoltage Vg is set to a voltage Vpv higher than that in reading, therebyperforming “0” reading. Then, a write operation and a program verifyoperation are carried out alternately. When all of the cells to bewritten into have the “0,” the writing operation is ended. Similarly, inerasing, a voltage Vev lower than the voltage in reading is applied tothe control gate CG, thereby carrying out a “1” reading erase verifyoperation, which secures the cell current Icell sufficiently. Asdescribed above, the word-line voltage to the cell varies according tothe operation mode.

[0013] With the recent improvements in the data processing speed of CPUs(Central Processing Units), flash memories are required to havehigher-speed data transmission speed. Such flash memory as shortens thetotal data output time of consecutive words by having a page modereading function as DRAM or SRAM has been put on the market (seeISSCC2001 DIGEST OF TECHNICAL PAPERS pp. 32-33, February 2001, B.Pathank et al., “A 1.8-V 64-Mb 100-MHz Flexible Read While Write FlashMemory”). A collection of words, that is, a page, is specified by a pageaddress. Any word on the page is specified by an intra-page address(in-page address). Since words on the page have consecutive addresses,the intra-page addresses are allocated to the column side. Therefore, ina case where low-order addresses are allocated to the column side,addresses higher in order than these addresses are allocated to the rowside, and addresses still higher in order are allocated to blockaddresses, when a program composed of several tens of to hundreds ofconsecutive words is read, the number of word lines to be selected issmaller than that in a conventional method of allocating low-orderaddresses to the row side, middle-order addresses to the column side,and high-order addresses to block addresses. As a result, the timeduring which reading stress per line is applied becomes longer, whichmakes it more difficult to maintain the data reliability.

[0014] For example, when cells for 32 words are connected to a singleword line, consider a case where 128 words continue to be read for tenyears. When there is no page mode function, since allocating thelow-order addresses to the rows makes it possible to read 128 word linesequally, the stress time per word line is 3×108 sec/128 words=3×10⁶ sec.On the other hand, when the page size is 8 words, four pages areallocated to a single word line and 128 words are allocated to four wordlines. As a result, since eight words can be read during the timerequired to read one word, the word line stress time with respect to thetime required to read eight words is ⅛. However, because the number ofword lines decreases to {fraction (4/128)}, the length of time that asingle word line is selected becomes 32 times the present value. As aresult, the word line stress time (or read disturb time) is four timesas long as that when there is no page mode.

[0015] As described above, the conventional nonvolatile semiconductormemory with a page mode reading function to realize high-speed datatransfer speed has the problem of increasing the read disturb time.Measures to deal with this problem have been needed.

BRIEF SUMMARY OF THE INVENTION

[0016] According to an aspect of the present invention, there isprovided a nonvolatile semiconductor memory comprising: a plurality ofnonvolatile memory cells, at least one of the plurality of nonvolatilememory cells is addressed by address signals Ai(i=0, . . . ,I−1), eachof the address signals Ai(i=0, . . . ,I−1) including first addresssubset Aj(j=0, . . . ,J−1), second address subset Ak(k=J, . . . ,K−1),and third address subset Al(l=K, . . . ,L−1); a plurality of word linesand a plurality of bit lines which are connected to the plurality ofnonvolatile memory cells; an address buffer to which the first addresssubset is inputted as a first column address, the second address subsetis inputted as a first row address, and a third address subset isinputted as a second column address; and a decoder to which the outputsignal of the address buffer is supplied and which is configured toselect at least one of the plurality of nonvolatile memory cells,wherein the plurality of bit lines are selected by at least the thirdaddress subset, and the plurality of word lines are selected by at leastthe second address subset.

[0017] According to another aspect of the present invention, there isprovided a nonvolatile semiconductor memory with at least as many senseamplifiers as correspond to 2 ^(N1) words comprising: a plurality ofnonvolatile memory cells; a plurality of word lines and a plurality ofbit lines which are connected to the plurality of nonvolatile memorycells; an address buffer to which an N1 number of address subset of thelowest order are inputted as a first column address, an N2 number ofaddress subset higher than any of the N1 number of address subset areinputted as a first row address, and an N3 number of address subsethigher in order than any of the N2 number of address subset are inputtedas a second column address; and a decoder to which the output signal ofthe address buffer is supplied and which is configured to select atleast one of the plurality of nonvolatile memory cells, wherein theplurality of bit lines are selected by at least the second columnaddress, and the plurality of word lines are selected by at least thefirst row address.

[0018] According to still another aspect of the present invention, thereis provided a nonvolatile semiconductor memory with at least as manysense amplifiers as correspond to 2 ^(N1) words comprising: a pluralityof nonvolatile memory cells; a plurality of word lines and a pluralityof bit lines which are connected to the plurality of nonvolatile memorycells; an address buffer to which an N1 number of address subset of thelowest order are inputted as an intra-page address, an N2 number ofaddress subset higher in order than any of the N1 number of addresssubset are inputted as a first row address, and an N3 number of addresssubset higher in order than any of the N2 number of address subset areinputted as a page address; and a decoder to which the output signal ofthe address buffer is supplied and which is configured to select atleast one of the plurality of nonvolatile memory cells, wherein theplurality of bit lines are selected by at least the page address, andthe plurality of word lines are selected by at least the first rowaddress.

[0019] According to still another aspect of the present invention, thereis provided a nonvolatile semiconductor memory comprising: a pluralityof nonvolatile memory cells; a plurality of word lines and a pluralityof bit lines which are connected to the plurality of nonvolatile memorycells; a first address buffer to which a first address subset isinputted; a second address buffer to which a second address subsethigher in order than the first address subset is inputted; a thirdaddress buffer to which a third address subset higher in order than thesecond address subset is inputted; a row decoder to which the output ofthe second address buffer is inputted and which selects one of theplurality of word lines when reading the data stored in the plurality ofnonvolatile memory cells; a column decoder to which the output of thethird address buffer is inputted and which selects at least an N (whereN is a positive integer equal to or larger than 2) number of bit linesfrom the plurality of bit lines when reading the data stored in theplurality of nonvolatile memory cells; at least an N number of senseamplifiers which read the data in the memory cells selected for reading;a multiplexer to which the output of the first address buffer isinputted and which selects an M number of outputs from the outputs ofthe N number of sense amplifiers; and an output buffer to which theoutput of the multiplexer is inputted.

[0020] According to still another aspect of the present invention, thereis provided a nonvolatile semiconductor memory comprising: a pluralityof nonvolatile memory blocks, each of which includes a plurality ofnonvolatile memory cells, a plurality of word lines and a plurality ofbit lines which are connected to the plurality of nonvolatile memorycells, a row decoder which selects one of the plurality of word lineswhen reading the data stored in the plurality of nonvolatile memorycells, and a column decoder which selects at least an N (where N is apositive integer equal to or larger than 2) number of bit lines from theplurality of bit lines when reading the data stored in the plurality ofnonvolatile memory cells; a first address buffer to which a firstaddress subset is inputted; a second address buffer to which a secondaddress subset higher in order than the first address subset isinputted; a third address buffer to which a third address subset higherin order than the second address subset is inputted; a fourth addressbuffer to which a fourth address subset higher in order than the thirdaddress subset is inputted; at least an N number of sense amplifierswhich read the data in the memory cells selected for reading; amultiplexer to which the output of the first address buffer is inputtedand which selects an M number of outputs from the outputs of the Nnumber of sense amplifiers; an output buffer to which the output of themultiplexer is inputted; and a block decoder to which the output of thefourth address buffer is inputted and which selects one of the pluralityof nonvolatile memory blocks when reading the data stored in theplurality of nonvolatile memory cells, wherein one of the word-lines isselected by the output of the second address buffer and the output ofthe block decoder, and at least one of the bit-lines is selected by theoutput of at least the third address buffer and the output of the blockdecoder.

[0021] According to still another aspect of the present invention, thereis provided a nonvolatile semiconductor memory comprising: a pluralityof nonvolatile memory blocks, each of which includes a plurality ofnonvolatile memory cells, a plurality of word lines and a plurality ofbit lines which are connected to the plurality of nonvolatile memorycells, a row decoder which selects one of the plurality of word lineswhen reading the data stored in the plurality of nonvolatile memorycells, and a column decoder which selects at least an N (where N is apositive integer equal to or larger than 2) number of bit lines from theplurality of bit lines when reading the data stored in the plurality ofnonvolatile memory cells; a first address buffer to which a firstaddress subset is inputted; a second address buffer to which a secondaddress subset higher in order than the first address subset isinputted; a third address buffer to which a third address subset higherin order than the second address subset is inputted; a fourth addressbuffer to which a fourth address subset higher in order than the thirdaddress subset is inputted; a fifth address buffer to which a fifthaddress subset higher in order than the fourth address subset isinputted; at least an N number of sense amplifiers which read the datain the memory cells selected for reading; a multiplexer to which theoutput of the first address buffer is inputted and which selects an Mnumber of outputs from the outputs of the N number of sense amplifiers;an output buffer to which the output of the multiplexer is inputted; anda block decoder to which the output of the fifth address buffer isinputted and which selects one of the plurality of nonvolatile memoryblocks when reading the data stored in the plurality of nonvolatilememory cells, wherein one of the word-lines is selected by the outputsof the second and fourth address buffers and the output of the blockdecoder, and at least one of the bit-lines is selected by the output ofat least the third address buffer and the output of the block decoder.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

[0022]FIG. 1 is a sectional view of a memory cell in a flash memory tohelp explain a conventional nonvolatile semiconductor memory;

[0023]FIG. 2 is a circuit diagram of a part of a memory cell array whereunits of the memory cell transistor of FIG. 1 are arranged in a matrix,which helps explain a conventional nonvolatile semiconductor memory;

[0024]FIG. 3 shows the relationship between the control gate voltage andthe drain current in the memory cell transistor of FIG. 1;

[0025]FIG. 4 is a block diagram schematically showing the configurationof a nonvolatile semiconductor memory according to an embodiment of thepresent invention;

[0026]FIG. 5 is a block diagram showing an layout image of a 2-bank16-Mbit flash memory with two redundancy blocks;

[0027]FIG. 6A is a circuit diagram showing the configuration of a columngate for selectively connecting a local bit line made of a first-levelmetal layer in a block to a main bit line made of a third-level metallayer;

[0028]FIG. 6B shows a symbol for the column gate shown in FIG. 6A;

[0029]FIG. 7A is a block diagram of a column gate including eight unitsof the column gate shown in FIGS. 6A and 6B;

[0030]FIG. 7B shows a symbol for the column gate shown in FIG. 7A;

[0031]FIG. 8A is a block diagram of a column gate;

[0032]FIG. 8B is a block diagram of a column redundancy column gate;

[0033]FIG. 8C shows a symbol for a column gate including 16 units of thecolumn gate shown in FIG. 8A and one unit of the column redundancycolumn gate shown in FIG. 8B;

[0034]FIG. 9A is a circuit diagram of a 512-Kbit memory cell array;

[0035]FIG. 9B shows a symbol for the memory cell array shown in FIG. 9A;

[0036]FIG. 10A is a circuit diagram of a 64-Kbit boot block cell array;

[0037]FIG. 10B shows a symbol for the boot block cell array shown inFIG. 10A;

[0038]FIG. 11A is a circuit diagram of a row decoder connected to eachword line;

[0039]FIG. 11B shows a symbol for the row decoder shown in FIG. 11A;

[0040]FIG. 12A is a block diagram of a row decoder controlled by apre-decode signal pair;

[0041]FIG. 12B shows a symbol for the row decoder shown in FIG. 12A;

[0042]FIG. 13 is a block diagram of a row decoder including 128 units ofthe row decoder shown in FIGS. 12A and 12B;

[0043]FIG. 14A is a circuit diagram of a pre-decoder that outputs apre-decode signal pair.;

[0044]FIG. 14B shows a symbol for the pre-decoder shown in FIG. 14A;

[0045]FIG. 15A is a block diagram of a row decoder including 128 unitsof the pre-decoder shown in FIGS. 14A and 14B;

[0046]FIG. 15B shows a symbol for the row decoder shown in. FIG. 15A;

[0047]FIG. 16A is a circuit diagram of a row decoder that drives aselected word line;

[0048]FIG. 16B shows a symbol for the row decoder shown in FIG. 16A;

[0049]FIG. 17A is a block diagram of a row decoder composed of eightunits of the row decoder shown in FIGS. 16A and 16B;

[0050]FIG. 17B shows a symbol for the row decoder shown in FIG. 17A;

[0051]FIG. 18A is a circuit diagram of a block decoder;

[0052]FIG. 18B shows a symbol for the block decoder shown in FIG. 18A;

[0053]FIG. 19A is a circuit diagram of a row decoder (signal BLKFigenerating circuit);

[0054]FIG. 19B shows a symbol for the row decoder shown in FIG. 19A;

[0055]FIG. 20A is a block diagram of a row decoder composed of eightunits of the row decoder shown in FIGS. 19A and 19B;

[0056]FIG. 20B shows a symbol for the row decoder shown in FIG. 20A;

[0057]FIG. 21A is a circuit diagram of a block decoder for boot blocks;

[0058]FIG. 21B shows a symbol for the block decoder shown in FIG. 21A;

[0059]FIG. 22A is a circuit diagram of a column decoder (signal BLKHigenerating circuit);

[0060]FIG. 22B shows a symbol for the column decoder shown in FIG. 22A;

[0061]FIG. 23A is a block diagram of a column decoder composed of fourunits of the column decoder shown in FIGS. 22A and 22B;

[0062]FIG. 23B shows a symbol for the column decoder shown in FIG. 23A;

[0063]FIG. 24A is a circuit diagram of a column decoder;

[0064]FIG. 24B shows a symbol for the column decoder shown in FIG. 24A;

[0065]FIG. 25A is a circuit diagram of a column gate that selectivelyconnects the main bit line to a read-only data line;

[0066]FIG. 25B shows a symbol for the column gate shown in FIG. 25A;

[0067]FIG. 26A is a block diagram of a column gate including 64 units ofthe column gate shown in FIGS. 25A and 25B;

[0068]FIG. 26B is a circuit diagram to help explain the connectionbetween the column redundancy main bit line for each bit and the columnredundancy data line;

[0069]FIG. 26C shows a symbol for the column gate including 64 units ofthe column gate shown in FIGS. 25A and 25B;

[0070]FIG. 27A is a circuit diagram of a column gate that decodes themain bit line in a write or a verify operation and selectively connectsthe main bit line to an auto-only data line;

[0071]FIG. 27B shows a symbol for the column gate shown in FIG. 27A;

[0072]FIG. 28A is a block diagram of a column gate composed of thecolumn gate shown in FIGS. 27A and 27B;

[0073]FIG. 28B is a circuit diagram to help explain the connectionbetween the column redundancy main bit line for each bit and A_RDDL;

[0074]FIG. 28C shows a symbol for the column gate composed of the columngate shown in FIGS. 27A and 27B;

[0075]FIGS. 29A and 29B are block diagrams of a pre-decoder thatselectively connects 128 main bit lines and a redundancy main bit lineto (64+1) read data lines and (16+1) auto data lines;

[0076]FIG. 29C shows a symbol for the column gate shown in FIGS. 29A and29B;

[0077]FIG. 30A is a circuit diagram of a decoder that outputs signalR_JHH;

[0078]FIG. 30B shows a symbol for the decoder shown in FIG. 30A;

[0079]FIG. 31A is a circuit diagram of a decoder for read column gateselect signals;

[0080]FIG. 31B shows a symbol for the decoder shown in FIG. 31A;

[0081]FIG. 32A is a block diagram of a decoder including three units ofthe decoder shown in FIGS. 31A and 31B;

[0082]FIG. 32B shows a symbol for the decoder shown in FIG. 32A;

[0083]FIG. 33A is a circuit diagram of a decoder for auto column gatesignals;

[0084]FIG. 33B shows a symbol for the decoder shown in FIG. 33A;

[0085]FIG. 34A is a circuit diagram of a decoder for auto column gatesignals;

[0086]FIG. 34B shows a symbol for the decoder shown in FIG. 34A;

[0087]FIG. 35A is a block diagram of a decoder for auto column gatesignals;

[0088]FIG. 35B shows a symbol for the decoder shown in FIG. 35A;

[0089]FIG. 36A is a circuit diagram of a decoder for column gateactivating signals for a bank including a boot block;

[0090]FIG. 36B shows a symbol for the decoder shown in FIG. 36A;

[0091]FIG. 37A is a circuit diagram of a decoder for column gateactivating signals for a bank including a boot block;

[0092]FIG. 37B shows a symbol for the decoder shown in FIG. 37A;

[0093]FIG. 38A is a block diagram of a decoder that outputs signalsR_BLKD<0:1>, R_BLKDRD, A_BLKD<0:7>, A_BLKDRD;

[0094]FIG. 38B shows a symbol for the decoder shown in FIG. 38A;

[0095]FIG. 39A is a block diagram of a decoder that outputs column gatesignals for a bank including a boot block;

[0096]FIG. 39B shows a symbol for the decoder shown in FIG. 39A;

[0097]FIG. 40A is a block diagram showing the connection between acolumn gate signal output for a bank including no boot and a decodercolumn gate;

[0098]FIG. 40B shows a symbol for the circuit shown in FIG. 40A;

[0099]FIG. 41A is a block diagram showing the connection between acolumn gate signal output for a bank including a boot and a decodercolumn gate;

[0100]FIG. 41B shows a symbol for the circuit shown in FIG. 41A;

[0101]FIGS. 42A and 42B are circuit diagrams of a global decoder forcolumn gate select signals;

[0102]FIGS. 43A and 43B are circuit diagrams of a global decoder forcolumn gate select signals;

[0103]FIG. 44 shows a symbol for the global decoder for column gateselect signals;

[0104]FIG. 45A is a block diagram of a global decoder to help explainthe connection relationship between a global column gate signal outputfor a bank including no boot block and a column decoder;

[0105]FIG. 45B is a block diagram of a column decoder to help explainthe connection relationship between a global column gate signal outputfor a bank including no boot block and a column decoder;

[0106]FIG. 45C shows a symbol for a decoder composed of the globaldecoder shown in FIG. 45A and the column decoder shown in FIG. 45B;

[0107]FIG. 46A is a block diagram of a global decoder to help explainthe connection relationship between a global column gate signal outputfor a bank including a boot block and a column decoder;

[0108]FIG. 46B is a block diagram of a column decoder to help explainthe connection relationship between a global column gate signal outputfor a bank including a boot block and a column decoder;

[0109]FIG. 46C shows a symbol for a decoder composed of the globaldecoder shown in FIG. 46A and the column decoder shown in FIG. 46B;

[0110]FIG. 47A is a block diagram showing a 512-Kbit block arrangement;

[0111]FIG. 47B shows a symbol for the block configuration shown in FIG.47A;

[0112]FIG. 48A is a block diagram of a 4-Mbit core 4MbCORE composed ofeight units of the 512-Kbit block shown in FIGS. 47A and 47B;

[0113]FIG. 48B shows a symbol for the core 4MbCORE shown in FIG. 48A;

[0114]FIG. 49A is a block diagram of a boot block;

[0115]FIG. 49B shows a symbol for the boot block shown in FIG. 49A;

[0116]FIG. 50A is a block diagram showing the connection relationshipbetween eight boot blocks;

[0117]FIG. 50B shows a symbol for the circuit shown in FIG. 50A;

[0118]FIG. 51 is a circuit diagram showing an example of theconfiguration of an address buffer, centering on bit i;

[0119]FIG. 52 is a circuit diagram of an address buffer;

[0120]FIG. 53 is a circuit diagram showing an example of theconfiguration of a bank signal generating circuit;

[0121]FIG. 54A is a circuit diagram showing an example of theconfiguration of a power switch;:

[0122]FIG. 54B shows a symbol for the power switch shown in FIG. 54A;

[0123]FIG. 55A is a circuit diagram showing an example of theconfiguration of a power switch;

[0124]FIG. 55B shows a symbol for the power switch shown in FIG. 55A;

[0125]FIG. 56A is a circuit diagram showing an example of theconfiguration of a power switch;

[0126]FIG. 56B shows a symbol for the power switch shown in FIG. 56A;

[0127]FIG. 57 is a circuit diagram showing an example of theconfiguration of a block redundancy control signal output circuit;

[0128]FIG. 58 is a circuit diagram showing an example of theconfiguration of a block redundancy control signal output circuit;

[0129]FIG. 59 is a circuit diagram of a circuit that generates mainblock addresses;

[0130]FIG. 60A is a block diagram showing an example of theconfiguration of a power switch and a decoder provided for each 4-Mbitcore;

[0131]FIG. 60B shows a symbol for the power switch and decoder shown inFIG. 60A;

[0132]FIG. 61A is a block diagram of a 4-Mbit power switch and a decoderwhich are composed of a 4-Mbit core and a power switch;

[0133]FIG. 61B shows a symbol for the power switch and decoder shown inFIG. 61A;

[0134]FIG. 62A is a block diagram of a power switch and decoder for aboot core;

[0135]FIG. 62B shows a symbol for the power switch and decoder shown inFIG. 62A;

[0136]FIG. 63A is a block diagram of a power switch and decoder for aboot core which are composed of a boot core and a power switch anddecoder for the boot core;

[0137]FIG. 63B shows a symbol for the power switch and decoder shown inFIG. 63A;

[0138]FIG. 64 is a block diagram showing the configuration of thedecoder of bank BANK 0;

[0139]FIG. 65 shows a symbol for the decoder of bank BANK 0 shown inFIG. 64;

[0140]FIG. 66A is a block diagram of the power switch and decoder ofbank BANK 1;

[0141]FIG. 66B shows a symbol for the power switch and decoder shown inFIG. 66A;

[0142]FIG. 67 is a block diagram showing the configuration of thedecoder of bank BANK 1;

[0143]FIG. 68 shows a symbol for the decoder of bank BANK 1 shown inFIG. 67;

[0144]FIG. 69A is a block diagram of a global decoder, showing the blockredundancy column decoder section;

[0145]FIG. 69B is a block diagram of a decoder, showing the blockredundancy column decoder section;

[0146]FIG. 69C shows a symbol for the block redundancy decoder,representing the block redundancy column decoder section;

[0147]FIG. 70A is a block diagram showing the connection relationshipbetween the redundancy block power switch and decoder and the block;

[0148]FIG. 70B shows a symbol for the circuit shown in FIG. 70A;

[0149]FIG. 71 is a block diagram showing the configuration of aredundancy block decoder;

[0150]FIG. 72 shows a symbol for the redundancy block decoder shown inFIG. 71;

[0151]FIGS. 73A to 73D are block diagrams showing the configuration of a16-Mbit flash memory with a 2-bank structure of 4-Mbit+12-Mbit includingtwo redundancy blocks;

[0152]FIG. 74 shows a symbol for the 16-Mbit flash memory core shown ineach of FIGS. 73A to 73D;

[0153]FIG. 75 is a circuit diagram showing an example of theconfiguration of a column redundancy circuit;

[0154]FIG. 76 is a circuit diagram of a sense amplifier and a circuitthat latches the sensed data;

[0155]FIG. 77 is a circuit diagram of a read and program verify senseamplifier;

[0156]FIG. 78 is a circuit diagram of a circuit that latches columnredundancy fuse data;

[0157]FIG. 79 is a circuit diagram of a circuit that latches columnredundancy fuse data;

[0158]FIG. 80 is a circuit diagram of a circuit that generates a signalfor causing a multiplexer to replace I/O data when outputting the wordwhose intra-page address coincides with the fuse data;

[0159]FIG. 81 is a circuit diagram of the multiplexer;

[0160]FIG. 82 is a circuit diagram of the multiplexer;

[0161]FIG. 83 is a circuit diagram showing an example of theconfiguration of a data latch circuit that latches program data;

[0162]FIG. 84 is a circuit diagram showing an example of theconfiguration of a sense latch circuit that verifies a program operationor an erase operation;

[0163]FIG. 85 is a circuit diagram showing an example of theconfiguration of a circuit that performs column redundancy in an autooperation;

[0164]FIG. 86 is a circuit diagram showing a circuit which outputs anend signal for designating the end of program when program data and averify result completely coincide with each other;

[0165]FIG. 87 is a circuit diagram of a circuit that transfers data onthe target I/O to PDATARD when column redundancy replacement isperformed;

[0166]FIG. 88 is a circuit diagram showing an example of theconfiguration of a program load circuit connected to an auto data line;

[0167]FIG. 89 is a timing chart for an operation waveform showing aprogram operation;

[0168]FIG. 90 is a timing chart for an operation waveform showing a readoperation;

[0169]FIGS. 91A and 91B are diagrams showing an example of first addressallocation in a nonvolatile semiconductor memory according to anembodiment of the present invention;

[0170]FIGS. 92A to 92C are diagrams showing an example of second addressallocation in a nonvolatile semiconductor memory according to anembodiment of the present invention;

[0171]FIGS. 93A and 93B are diagrams showing an example of third addressallocation in a nonvolatile semiconductor memory according to anembodiment of the present invention;

[0172]FIGS. 94A to 94C are diagrams showing an example of fourth addressallocation in a nonvolatile semiconductor memory according to anembodiment of the present invention;

[0173]FIGS. 95A and 95B are diagrams showing an example of fifth addressallocation in a nonvolatile semiconductor memory according to anembodiment of the present invention;

[0174]FIGS. 96A to 96C are diagrams showing an example of sixth addressallocation in a nonvolatile semiconductor memory according to anembodiment of the present invention;

[0175]FIG. 96D is a circuit diagram illustrating an i-th bit buffercircuit incorporated in the address buffer;

[0176]FIG. 96E is a symbolic view of the buffer circuit shown in FIG.96D;

[0177]FIG. 96F is a block diagram illustrating structural examples ofthe address buffer of FIG. 4;

[0178]FIGS. 97A and 97B are diagrams showing an example of seventhaddress allocation in a nonvolatile semiconductor memory according to anembodiment of the present invention; and

[0179]FIGS. 98A to 98C are diagrams showing an example of eighth addressallocation in a nonvolatile semiconductor memory according to anembodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0180]FIG. 4 is a block diagram schematically showing the configurationof a nonvolatile semiconductor memory according to an embodiment of thepresent invention. The nonvolatile semiconductor memory comprises amemory cell array 11, a row decoder 12, a column decoder 13, a blockdecoder 14, column gates 15, a sense amplifier 16, a program circuit 17,charge pumps 18, a voltage switch 19, an I/O buffer 20, a controller 21,a command register 22, and an address buffer 23.

[0181] An address signal ADD inputted to the address buffer 23 issupplied to the row decoder 12, the column decoder 13, and block decoder14. In addition, part of the address signal ADD is supplied to thecommand register 22. Write data WDA supplied to the I/O buffer 20 issupplied to the program circuit 47. Command CMD is supplied to thecommand register 22. The output of the command register 22 is suppliedto the controller 21, which decodes the output. The controller 21controls the sense amplifier 16, program circuit 17, charge pump 18,voltage switch 19 and address buffer 23. The output voltages Vddh, Vddr,Vbb of the charge pumps 18 are supplied to the voltage switch 19, columndecoder 13, and block decoder 14, respectively. The output voltage Vddpis supplied to the program circuit 17. The output voltages VSWi and VBBiof the voltage switch 19 are supplied to the row decoder 12.

[0182] The write data WDA supplied to the program circuit 17 passesthrough the column gates 15 selected by the column decoder 13 and issupplied to bit lines BLs of the memory cell array 11. Then, the writedata WDA is written into the memory cells connected to the intersectionsof the bit line BLs and word line WLs selected by the row decoder 12. Atthis time, the block to be written into is specified by the blockdecoder 14.

[0183] On the other hand, the data read from the memory cells selectedby the row decoder 14, column decoder 13, and block decoder 14 passesthrough the column gates 15 and is supplied to the sense amplifier 16,which senses and amplifies the data. The resulting data is read via theI/O buffer 20.

[0184]FIG. 5 shows a more detailed configuration of the nonvolatilesemiconductor memory shown in FIG. 4, giving a layout image of a 16-Mbitflash memory with a 2-bank structure including two redundancy blocks.Eight blocks are arranged in the X direction, starting from the powerswitch and decoder VolDec. The signals Mi/MiB, Fi, Hi outputted from thepower switch and decoder VolDec are wired at a second-level metal layer(metal2) passing over cell array CellArray. On the other hand, a localbit line is wired at a first-level metal layer and a global bit line iswired at a third-level metal layer (metal3). The global bit linecommonly connects to three blocks for bank 0 in the Y direction from asecond-stage column decoder ColDec8. It further commonly connects to ablock and a boot block for bank 1. The main bit line connected to theselected column decoder ColDec8 is connected to a common data line. Thelocal bit line of a redundancy block is connected to a data line inreplacement.

[0185] Next, the configuration of each block in the layout image of FIG.5 will be explained.

[0186]FIG. 6A is a circuit diagram of column gate 1stCOL1 forselectively connecting local bit lines LBL0 to LBL3 in a block made ofthe first-level metal layer to the main bit line MBL made of thethird-level metal layer. FIG. 6B shows a symbol for column gate 1stCOL1shown in FIG. 6A. As shown in FIG. 6A, column gate 1stCOL1 is composedof transistors BQ0 to BQ3 to whose gates decode signals BLKH0 to BLKH3from column decoder ColDec1 are supplied. One end of the current path oftransistors BQ0 to BQ3 is connected to local bit lines LBL0 to LBL3. Theother end of the current path of transistors BQ0 to BQ3 is connected tomain bit line MBL.

[0187]FIG. 7A is a block diagram of column gate 1stCOL2 including eightunits of the column gate 1stCOL1 shown in FIGS. 6A and 6B. FIG. 7B showsa symbol for the column gate 1stCOL2. The column gate 1stCOL2 isprovided so as to correspond to each I/O.

[0188]FIGS. 8A to 8C each show a column gate. Specifically, column gate1stCOL3 (FIG. 8C) includes as many column gates 1stCOL2 as is equivalentto the word width, that is, 16 units of column gate 1stCOL2 (FIG. 8A),and a single column redundancy column gate 1stCOL1 (FIG. 8B). The columnredundancy column gate 1stCOL1, which has four local bit lines (RDLBL0to RDLBL3) and a single main bit line (RDMBL), is capable of controllingthe column select signal by using the same signals H0 to H3 as those inthe main body. Column gate 1stCOL3 shown in FIG. 8C decodes 512 localbit lines and four column redundancy bit lines in the main body into 128main bit lines and one column redundancy bit line.

[0189]FIG. 9A is a circuit diagram of a 512-Kbit memory cell arrayCellArray. FIG. 9B shows a symbol for the 512-Kbit memory cell arrayCellArray. As shown in FIG. 9A, memory cell transistors MC are arrangedin a 516×1024 matrix including redundancy transistors. The control gatesof the individual memory cell transistors MC-are connected to word linesWL0 to WL1023 on a row basis. The drains of the memory cell transistorsMC are connected to local bit lines LBL0 to LBL511 and redundancy localbit lines RDLBL0 to RDLBL3 on a column basis. The sources of the memorycell transistors MC are commonly connected to a source line SL.

[0190]FIG. 10A is a circuit diagram of a 64-Kbit boot block cell arrayBootCellArray. FIG. 10B shows a symbol for the 64-Kbit boot block cellarray BootCellArray. As shown in FIG. 10A, 128 word lines are providedand the columns have the same arrangement as that of the main body.Specifically, memory cell transistors MC are arranged in a 516×128matrix including redundancy transistors. The control gates of theindividual memory cell transistors MC are connected to word lines WL0 toWL127 on a row basis. The drains of the memory cell transistors MC areconnected to local bit lines LBL0 to LBL511 and redundancy local bitlines RDLBL0 to RDLBL3 on a column basis. The sources of the memory celltransistors MC are commonly connected to a source line SL.

[0191]FIG. 11A is a circuit diagram of row decoder RowDec0 connected toeach word line. FIG. 11B shows a symbol for row decoder RowDec0. Asshown in FIG. 11A, row decoder RowDec0 is composed of a transfer gatemade up of an n-channel transistor n1 and a p-channel transistor p1 andan n-channel transistor n2. The transfer gate, which is controlled by apre-decode signal pair Mi/MiB, determines whether to supply signal BLKFjto word line WLi,j. The pre-decode signal MiB is supplied to the gate oftransistor n2, thereby performing on/off control of transistor n2. Whenword line WLi,j is not selected, transistor n2 is designed to produce anunselected word line potential VBBi.

[0192]FIGS. 12A and 12B each shows a row decoder controlled bypre-decode signal pair Mi/MiB. Row decoder RowDec1 shown in FIG. 12B iscomposed of eight units of row decoder RowDec0 shown in FIG. 12A, withadjacent eight word lines being controlled by the same pre-decode signalpair Mi/MiB.

[0193]FIG. 13 shows a row decoder RowDec2 including 128 units of rowdecoder RowDec1 shown in FIGS. 12A and 12B. The 1024 word lines in the512-Kbit memory cell array CellArray are decoded by a combination of 8signals BLKFi and 128 pre-decode signal pairs Mi/MiB.

[0194]FIG. 14A is a circuit diagram of pre-decoder RowDec3 that outputspre-decode signal pair Mi/MiB. FIG. 14B shows a symbol for pre-decoderRowDec3. As shown in FIG. 14A, the pre-decoder RowDec3 includes an ANDgate AND1 to which erase signal ERASEB and row address RA<3:9> aresupplied and a level shifter LS1 that operates on voltages VSWi andVBBi. Level shifter LS1 is designed to output pre-decode signal pairMi/MiB.

[0195]FIG. 15A is a circuit diagram of pre-decoder RowDec4 that includes128 pairs of pre-decoder RowDec3 shown in FIGS. 14A and 14B. FIG. 15Bshows a symbol for pre-decoder RowDec4. The 128 pre-decode signal pairsMi/MiB are decode signals for seven row addresses RA<3:9>. In an eraseoperation, erase signal ERASEB goes low, which brings all of the 128pre-decode signal pairs Mi/MiB into the unselected state.

[0196]FIG. 16A is a circuit diagram of row decoder RowDec5 that drivesthe selected word line. FIG. 16B shows a symbol for row decoder RowDec5.As shown in FIG. 16A, row decoder RowDec5 includes an AND gate AND2 towhich erase signal ERASEB and row address RA<0:2> are supplied and alevel shifter LS2 that operates on voltages VSWi and VBBi. Row decoderRowDec5 decodes row address RA<0:2> and causes level shifter LS tooutput signal Fi.

[0197]FIG. 17A is a circuit diagram of row decoder RowDec6 composed ofeight units of row decoder RowDec5 shown in FIGS. 16A and 16B. FIG. 17Bshows a symbol for row decoder RowDec6.

[0198]FIG. 18A is a circuit diagram of block decoder BlockDec. FIG. 18Bshows a symbol for block decoder BlockDec. As shown in FIG. 18A, blockdecoder BlockDec includes AND gates AND3, AND4, level shifters LS3 toLS6, and an inverter INV1. Block address BA<0:2> is supplied to AND gateAND3. The output signal of AND gate AND3 is supplied to one inputterminal of each of level shifter LS3, level shifter LS4, and AND gateAND4. Erase signal ERASE (a signal whose phase is opposite to that oferase signal ERASEB) is supplied to the other input terminal of AND gateAND4. The output signal of AND gate AND 4 is supplied to level shifterLS5 and level shifter LS6.

[0199] Level shifter LS3, which operates on voltages VSWi and VBBi,outputs signal BSH. Level shifter LS4, which operates on voltages VSWCiand GND, outputs signal BSHH. Level shifter LS5, which operates onvoltages VSWCi and GND, drives cell source line SLi of block i. Levelshifter LS6 operates on voltages VSWi and VBBi. The output of levelshifter LS6 passes through inverter INV1 operating on voltages GND, VBBiand is supplied as signal VBBBi.

[0200] That is, block decoder BlockDec decodes block address BA<0:2>into different-level signals BSH and BSHH. Furthermore, when the erasureof block i is selected, bock decoder BlockDec applies voltage VSWCi tothe cell source line SLi of block i. Signal VBBBi, which is for applyingan unselected word line potential, goes to VBBi level when erasure isselected.

[0201]FIG. 19A is a circuit diagram of row decoder RowDec7 (a signalBLKFi generating circuit). FIG. 19B shows a symbol for Row decoderRowDec7. Row decoder RowDec7, which is composed of an AND gate AND5operating on voltages VSWi and VBBi, generates signal BLKFI from thelogical product of signal Fi and signal BSH.

[0202]FIG. 20A is a block diagram of row decoder RowDec8 composed ofeight units of row decoder RowDec7 shown in FIGS. 19A and 19B. FIG. 20Bshows a symbol for Row decoder RowDec8.

[0203]FIG. 21A is a circuit diagram of block decoder BootBlockDec forboot blocks. FIG. 21B shows a symbol for block decoder BootBlockDec. Asshown in FIG. 21A, block decoder BootBlockDec includes AND gates AND6,AND7, level shifters LS7 to LS10, and an inverter INV2. Row addressRA<7:9> and block address BA<0:2> are supplied to AND gate AND6. Theoutput signal of AND gate AND6 is supplied to one input terminal of eachof level shifter LS7, level shifter LS8, and AND gate AND7. Erase signalERASE is supplied to the other input terminal of AND gate AND7. Theoutput signal of AND gate AND7 is supplied to level shifter LS9 andlevel shifter LS10.

[0204] Level shifter LS7, which operates on voltages VSWi and VBBi,outputs signal BSH. Level shifter LS8, which operates on voltages VSWCiand GND, outputs signal BSHH. Level shifter LS9, which operates onvoltages VSWCi and GND, drives cell source line SL. Level shifter LS10operates on voltages VSWi and VBBi. The output of level shifter LS10passes through inverter INV2 operating on voltages GND, VBBi and issupplied as signal VBBBi.

[0205] With the above configuration, when all of the row addressesRA<7:9> go high, a boot block is selected. Eight boot blocks BootBLK areselected by row addresses RA<7:9>.

[0206]FIG. 22A is a circuit diagram of column decoder ColDec1 (signalBLKHi generating circuit). FIG. 22B shows a symbol for column decoderColDec1. Column decoder ColDec1, which is composed of an AND gate AND8operating on voltages VSWCi and GND, generates signal BLKHi from thelogical product of signal BSHH and signal Hi.

[0207]FIG. 23A is a circuit diagram of column decoder ColDec2. FIG. 23Bshows a symbol for column decoder ColDec2. Column decoder ColDec2 iscomposed of four-units of column decoder ColDec1. Signal H<0:3> isobtained by level-converting the decode signal of column addressCA<3:4>.

[0208]FIG. 24A is a circuit diagram of column decoder ColDec3. FIG. 24Bshows a symbol for column decoder ColDec3. Column decoder ColDec3 iscomposed of an AND gate AND9 to which column address CA<3:4> is suppliedand a level shifter LS11 to which the output signal of AND gate AND9 issupplied and which operates on voltages VSWCi and GND. Column decoderColDec3 generates signal H<0:3>.

[0209] Main bit lines MBL0, MBL1 are selectively connected to read-onlydata line R_DL by column gate 2ndCOL1 as shown in FIGS. 25A and 25B.FIG. 25A is a circuit diagram of column gate 2ndCOL1. FIG. 25B shows asymbol for column gate 2ndCOL1. As shown in FIG. 25A, column gate2ndCOL1 includes transistor RQ0 and transistor RQ1. One end of thecurrent path of transistor RQ0 is connected to main bit line MBL0. Theother end of the current path of transistor RQ0 is connected toread-only data line R_DL. Read column gate select signal R_BLKD0 issupplied to the gate of transistor RQ0. One end of the current path oftransistor RQ1 is connected to main bit line MBL1. The other end of thecurrent path of transistor RQ1 is connected to read-only data line R_DL.Read column gate select signal R_BLKD1 is supplied to the gate oftransistor RQ1.

[0210] When the page length is four words, or 64 bits, decoding iseffected by column gate 2ndCOL2 composed of 64 units of column gate2ndCOL1 shown in FIGS. 25A and 25B. As shown in FIG. 26B, columnredundancy main bit line RDMBL for each bit is connected to columnredundancy data line R_RDDL via the current path of transistor RQ3 towhose gate signal R_BLKDRD is supplied.

[0211]FIG. 27A is a circuit diagram of column gate 2ndCOL3 that decodesthe signals on main bit lines MBL0 to MBL7 in a program operation or averify operation and selectively connects the decoded signal toauto-only data line A_DL. FIG. 27B shows a symbol for column gate2ndCOL3. As shown in FIG. 27A, column gate 2ndCOL3 includes transistorsAQ0 to AQ7. One end of the current path of each of transistors AQ0 toAQ7 is connected to the corresponding one of main bit lines MBL0 toMBL7. The other end of the current path of each of transistors AQ0 toAQ7 is connected to auto-only data line A_DL. Signals A_BLKD0 to A_BLKD7are supplied to the gates of transistors AQ0 to AQ7, respectively.

[0212]FIG. 28A is a block diagram of column gate 2ndCOL4 composed ofcolumn gate 2ndCOL3 shown in FIGS. 27A and 27B. FIG. 28B is a circuitdiagram to help explain the connection between column redundancy bitline for each bit and A_RDDL. FIG. 28C shows a symbol for column gate2ndCOL4.

[0213]FIGS. 29A and 29B are block diagrams of column gate 2ndCOL5 thatselectively connects 128 main bit lines MBL<0:127> and one redundancymain bit line RDMBL to (64+1) read data lines and (16+1) auto datalines. FIG. 29C shows a symbol for column gate 2ndCOL5.

[0214]FIG. 30A is a circuit diagram of decoder McolDec1 that outputssignal R_JHH. FIG. 30B shows a symbol for decoder McolDec1. As shown inFIG. 30A, decoder McolDec1 is composed of an AND gate AND10 to whichread target bank signal R_BANKi and read block address signal R_BA<0:2>are supplied and a level shifter LS12 operating on voltages VSWCi andGND. Therefore, signal R_JHH is given in the form of decoded signals ofread target bank signal R_BANKi and read block address signal R_BA<0:2>.

[0215]FIG. 31A is a circuit diagram of decoder McolDec2 that outputsread column gate select signal R_BLKDi. FIG. 31B shows a symbol fordecoder McolDec2. Decoder McolDec2 operates on voltages VSWCi and GND.Decoder McolDec2, which is composed of the AND gate AND12 to whichsignal R_JHH and signal R_GDi outputted from decoder McolDec1 shown inFIGS. 30A and 30B are supplied, outputs read column gate select signalR_BLKDi.

[0216]FIG. 32A is a block diagram of decoder McolDec3 including threeunits of decoder McolDec2. FIG. 32B shows a symbol for decoder McolDec3.

[0217] Similarly, FIGS. 33A and 33B to FIGS. 35A and 35B show decodersMcolDec4, McolDec5, McolDec6 for auto column gate signals, respectively.Although the input signals and output signals are different, thesedecoders have basically the same configuration as that in FIGS. 30A and30B to FIGS. 32A and 32B. That is, decoder McolDec4 is composed of ANDgate AND13 and level shifter LS13. Decoder McolDec5 is composed of ANDgate AND14. Decoder McolDec6 is composed of nine units of decoderMcolDec5.

[0218]FIGS. 36A and 36B and FIGS. 37A and 37B show decoder McolDec1Bootand decoder McolDec4Boot for column gate activating signals for banksincluding boot blocks, respectively. As shown in FIG. 36A, decoderMcolDec1Boot includes an AND gate AND14 to which signal R_MBLKBOOT andsignal R_RA<7:9> are supplied, an AND gate AND15 to which signalR_MBLK<3> and signal R_BA<0:2> are supplied, an OR gate OR1 to which theoutput signals of AND14 and AND15 are supplied, and a level shiftcircuit LS14 that operates on voltages VSWCi, GND and shifts the levelof the output signal of OR gate OR1. Then, level shift circuit LS14outputs signal R_JHH.

[0219] As shown in FIG. 37A, decoder McolDec4Boot includes an AND gateAND16 to which signal A_MBLKBOOT and signal A_RA<7:9> are supplied, anAND gate AND17 to which signal A_MBLK<3> and signal A_BA<0:2> aresupplied, an OR gate OR2 to which the output signals of AND16 and AND17are supplied, and a level shift circuit LS15 that operates on voltagesVSWCi and GND, and shifts the level of the output signal of OR gate OR2.Then, level shift circuit LS15 outputs signal A_JHH. FIGS. 36B and 37Bshow symbols for decoder McolDec1Boot and McolDec4Boot, respectively.

[0220]FIG. 38A is a block diagram of decoder McolDec7 that outputssignals R_BLKD<0:1>, R_BLKDRD, A_BLKD<0:7>, A_BLKDRD. FIG. 38B shows asymbol for decoder McolDec7. As shown in FIG. 38A, decoder McolDec7 iscomposed of decoders McolDec1 and McolDec3 connected to each other anddecoders McolDec4 and McolDec6 connected to each other.

[0221]FIG. 39A is a block diagram of decoder McolDec7Boot that outputs acolumn gate signal for a bank including a boot block. FIG. 39B shows asymbol for decoder McolDec7Boot. As shown in FIG. 39A, decoderMcolDec7Boot is composed of decoders McolDec1Boot and McolDec3 connectedto each other and decoders McolDec4Boot and McolDec6 connected to eachother.

[0222]FIGS. 40A and 40B and FIGS. 41A and 41B show the connectionrelationship between the column gate signal output and the decodercolumn gate for a bank including no boot block and for a bank includinga boot block. FIGS. 40A and 41A are block diagrams showing theconfiguration. FIGS. 40B and 41B show symbols for the respectiveconfigurations. As shown in FIG. 40A, decoder ColDec8 is so constructedthat the output terminal of decoder McolDec7 is connected to the inputterminal of decoder 2ndCOL5. Furthermore, as shown in FIG. 41A, decoderColDec8Boot is so constructed that the output terminal of decoderMcolDec7Boot is connected to the input terminal of decoder 2ndCOL5.

[0223]FIGS. 42A, 42B, 43A and 43B are circuit diagrams of global decoderColGlobalDec for column gate select signals that generates respectivedecode signals. FIG. 44 shows a symbol for global decoder ColGlobalDec.FIG. 42A shows a circuit section that generates signal R_GD<0:1>, FIG.42B shows a circuit section that generates signal R_GDRD, FIG. 43A showsa circuit section that generates signal A_GD<0:7>, and FIG. 43B shows acircuit section that generates signal A_GDRD. Each circuit sectionincludes AND gates (AND18 to AND21) and level shifters (LS16 to LS19).

[0224]FIGS. 45A to 45C and FIGS. 46A to 46C show the connectionrelationship between the global column gate signal output and the columndecoder for a bank including no boot block and for a bank including aboot block. The output signals R_GD<0:1>, R_GDRD, A_GD<0:7>, A GDRD ofglobal decoder ColGlobalDec shown in FIG. 45A are supplied to columndecoder ColDec8 shown in FIG. 45B. Column decoder ColDec8 drives mainbit lines and redundancy main bit lines MBL0<0:127>, REMBL0, . . . ,MBL7<0:127>, RDMBL7. FIG. 45C shows a symbol for decoder ColDec9composed of global decoder ColGlobalDec and column decoder ColDec8.

[0225] The output signals R_GD<0:1>, R_GDRD, A_GD<0:7>, A_GDRD of globaldecoder ColGlobalDec shown in FIG. 46A are supplied to column decoderColDec8Boot shown in FIG. 46B. Column decoder ColDec8Boot drives mainbit lines and redundancy main bit lines MBL0<0:127>, REMBL0, . . . ,MBL7<0:127>, RDMBL7. FIG. 46C shows a symbol for decoder ColDec9Bootcomposed of global decoder ColGlobalDec and column decoder ColDec8Boot.

[0226]FIG. 47A shows the configuration of a 512-Kbit block. FIG. 47Bshows a symbol for the 512-Kbit block. As shown in FIG. 47A, block BLKis comprised of a cell array CellArray, a first-stage column gate1stCol3, a decoder ColDec2 for the first-stage column gate 1stCol3, rowdecoders RowDec2 and RowDec8, and a block decoder BlockDec.

[0227]FIG. 48A shows the configuration of a 4-Mbit core 4MbCORE composedof eight units of the 512-Kbit block. FIG. 48B shows a symbol for the4-Mbit core 4MbCORE. These eight blocks share voltages VSWCi, VSWi,VBBi, and signals Mi/MiB, Fi, Hi. Main bit lines MBL<0:127>, MBLRD areprovided independently for the eight blocks.

[0228]FIG. 49A is a block diagram of boot block BootBLK. FIG. 49B showsa symbol for boot block BootBLK. The book block BootBLK differs fromblock BLK in that the total number of word lines is ⅛ that in block BLK,the number of RowDec2 is ⅛ that in block BLK, and the number of signallines for transferring pre-decode signal pairs Mi/MiB is ⅛ that in blockBLK, or 16.

[0229]FIGS. 50A and 50B show the connection relationship between eightboot blocks BootBLK. These boot blocks BootBLK share voltages VSWCi,VSWi, VBBi, and Signals Mi/MiB, Fi, Hi. Main bit lines MBL<0:127> andMBLRD are provided independently for the eight blocks.

[0230]FIG. 51 is a circuit diagram showing the configuration of anaddress buffer, centering on bit i. The address buffer is composed ofbuffer circuits BAC1, BAC2, clocked inverters CINV1, CINV2, and aninverter INV3. Signal BUSY goes high in a program operation or an eraseoperation. Auto addresses A_BA, RA, CA do not accept a change in addresspad Ai during an auto operation. R_BA, CA, RA indicate read addresses.Block high-order address BA<3:4> is decoded into main block addressMBLK<0:3> whose timing is controlled by signal BUSY or signal READE (inthis embodiment, a 16-Mbit flash memory is used as an example).

[0231]FIG. 52 is a circuit diagram of an address switch. The addressswitch is composed of AND gates AND22, AND23 and AND24, transfer gatesTG1 and TG2, inverters INV4a and INV4b, and an n-channel transistor Q4.The address switch is provided for each of the 4-Mbit cores 4MbCOREs orboot cores BootCORE. When the selected block is not replaced with blockredundancy, signal A_HITBLKB or signal R_HITBLKB goes high, with theresult that addresses BA, RA, CA of the selected 4MbCORE or BootCOREbecome A_BA, RA, CA in an auto operation and R_BA, RA, CA in a readoperation. All of the address signals of the unselected 4MbCORE orBootCORE go low.

[0232]FIG. 53 shows an example of the configuration of a bank signalgenerating circuit. In this embodiment, a 2-bank structure is used as anexample. The high-order 4 Mbits (BA<3>=BA<4>=H) in a block addressbelong to a first bank BANK1. The remaining 12 Mbits belong to a secondbank BANK0. There are two types of signal BANK, one for an autooperation and the other for a read operation.

[0233]FIGS. 54A, 54B, 55A, 55B, 56A and 56B show power switches VolSW1,VolSW2, and VolSW3, respectively. FIGS. 54A, 55A, and 56A are circuitdiagrams of power switches VolSW1, VolSW2 and VolSW3, respectively.FIGS. 54B, 55B and 56B show symbols for power switches VolSW1, VolSW2,and VolSW3, respectively. As shown in FIG. 54A, power switch VolSW1 iscomposed of a level shifter LS20 and p-channel MOS transistors Q5, Q6.As shown in FIG. 55A, power switch VolSW2 is composed of a level shifterLS21 and p-channel MOS transistors Q7 and Q8. As shown in FIG. 56A,power switch VolSW3 is composed of a level shifter LS22 and p-channelMOS transistors Q9 and Q10. Column power supply VSWC is switched on abank basis. Row power supplies VSW and VBB are switched on a 4-Mbit core4MbCORE basis or a boot core BootCORE basis.

[0234]FIGS. 57 and 58 each show an example of the configuration of ablock redundancy control signal output circuit. In each example, tworedundancy blocks are used. When the data coincides with redundancyaddress storage fuse data BA_FUSE0<0:4> or BA_FUSE1<0:4>, signal HITBLKgoes high. There are two types of signal HITBLK, one for an autooperation and the other for a read operation.

[0235]FIG. 59 shows a circuit that generates main block addresses. Themain block address signal MBLK outputted from this circuit is a signalfor selecting either 4-Mbit core 4MbCORE or boot core BootCORE.

[0236]FIGS. 60A and 60B show an example of the configuration of a powerswitch and decoder VolDec provided for each 4-Mbit core 4MbCORE. Asshown in FIG. 60A, the power switch and decoder VolDec includes powerswitch VolSW2, power switch VolSW3, row decoder RowDec4, row decoderRowDec6, and column decoder ColDec 3.

[0237]FIG. 61A is a block diagram of a 4-Mbit power switch and decoder4MbCoreVolDec which is composed of 4-Mbit core 4MbCORE and the powerswitch and decoder VolDec. FIG. 61B shows a symbol for the 4-Mbit powerswitch and decoder 4MbCoreVolDec. The power switch and decoder4MbCoreVolDec is designed to suppress fluctuations in the parasiticcapacitance of the power supply, regardless of whether redundancy isselected or not, by making the address on the main body side unselectedand setting the main body power switch in the selected state whenselecting block redundancy.

[0238] As shown in FIG. 52, when block redundancy is used (HITBLK=H),all of the input addresses to the decoder are made unselected, novoltage is applied to the memory cells. On the other hand, the powerswitches VolSW2 and VolSW3 shown in FIGS. 55 and 56 are put in theselected state, regardless whether redundancy replacement is performedor not. This is done to make the parasitic capacitance of the powersupplies VSW and VBB as constant as possible. Specifically, in a casewhere the power switch is also put in the unselected state on the basisof redundancy information, when a redundancy block is selected, aparasitic capacitance for one block develops. When no redundancy blockis selected, a parasitic capacitance for eight blocks develops. Thedifference between them is relatively large. A rewrite voltage isgenerated by a step-up circuit. Its rise time depends largely on theparasitic capacitance. The parasitic capacitance changes greatly,depending on whether redundancy is selected or not, which causes therise time to change greatly. As a result, the effective rewrite timechanges. This means that the rewrite condition changes, depending onwhether a redundancy block is selected or not, which causes a problem.

[0239] On the other hand, in a case where the power switch is put in theselected state, regardless of redundancy information, when a redundancyblock is selected, a parasitic capacitance for nine blocks develops. Incontrast, when no redundancy block is selected, a parasitic capacitancefor eight blocks develops. The difference between them is relativelysmall. As a result, the rewrite condition changes less, depending onwhether a redundancy block is selected or not, which causes no problemin terms of characteristic.

[0240] Therefore, with this configuration, fluctuations in the parasiticcapacitance are small, with the result that the rewrite condition forthe cells in the redundancy block is almost equal to that for the mainbody cells.

[0241]FIG. 62A is a block diagram of a boot core power switch anddecoder VolDecBoot. FIG. 62B shows a symbol for the boot core powerswitch and decoder VolDecBoot. As shown in FIG. 62A, the boot core powerswitch and decoder VolDecBoot includes a power switch VolSW2, a powerswitch VolSW3, a boot block row decoder RowDec4Boot, a row decoderRowDec6, and a column decoder ColDec3.

[0242]FIG. 63A is a block diagram of a boot core power switch anddecoder BootCoreVolDec composed of the boot core BootCORE and the bootcore power switch and decoder VolDecBoot. FIG. 63B shows a symbol forthe boot core power switch and decoder BootCoreVolDec. As shown in FIG.63A, the boot core power switch and decoder BootCoreVolDec is such thatthe output signals of the boot core power switch and decoder VolDecBootare supplied to boot core BootCORE.

[0243]FIG. 64 shows the configuration of the decoder of bank BANK0. BankBANK0 is composed of a power switch VolSW1, a 4-Mbit power switch anddecoder 4MbCoreVolDec, and a decoder ColDec9.

[0244]FIG. 65 shows a symbol for the decoder of bank BANK0 shown in FIG.64. FIG. 65 shows the configuration of the core of bank BANK0. In thisexample, one 4-Mbit section and boot section share the main bit line.

[0245]FIG. 66A is a block diagram of the power switch and decoderBanklCoreVolDec of bank BANK1. FIG. 66B shows a symbol for the powerswitch and decoder BanklCoreVolDec. As shown in FIG. 66A, the powerswitch and decoder BanklCoreVolDec is composed of a 4-Mbit power switchand decoder 4MbcoreVolDec and a boot core power switch and decoderBootCoreVolDec.

[0246]FIG. 67 shows the configuration of the decoder of BANK1. The bankBANK1 is composed of a power switch VolSW1, a power switch and decoderBanklCoreVolDec, and a boot decoder ColDec9Bboot.

[0247]FIG. 68 shows a symbol for the decoder of bank BANK1 shown in FIG.67. FIG. 68 shows the configuration of the core of bank BANK1.

[0248]FIGS. 69A to 69C show a block redundancy column decoder section.This column decoder section includes a global decoder ColGlobalDec shownin FIG. 69A, a decoder ColDec8 shown in FIG. 69B, and a block redundancydecoder ColDec9B shown in FIG. 69C.

[0249] On the main body side, a global decoder ColGlobalDec is providedfor eight blocks. A redundancy block is provided for a 512-Kbit block soas to be replaced with any block.

[0250]FIGS. 70A and 70B show the connection relationship between theredundancy block power switch and decoder VolDec and the block BLK. FIG.70A is a block diagram of the power switch and decoder VolDec and theblock BLK. FIG. 70B shows a symbol for the connection circuitBLKRDVolDec.

[0251]FIG. 71 shows the configuration of the decoder of a redundancyblock. The decoder includes the power switch VolSW1 shown in FIGS. 54Aand 54B, the connection circuit BLKRDVolDec between the redundancy blockpower switch and decoder VolDec and the block BLK shown in FIGS. 70A and70B, and a block redundancy decoder ColDec9BLKRD.

[0252] As described above, in the redundancy block, the power switch,row decoder, and column decoder are for exclusive use.

[0253]FIG. 72 shows a symbol for the redundancy block decoder RDBLKshown in FIG. 71.

[0254]FIGS. 73A to 73D are block diagrams of 16-Mbit flash memory coreswith a 2-bank structure of 4 Mbits+12 Mbits, including two redundancyblocks. The two redundancy blocks and two banks share (64+1) read datalines and (16+1) auto data lines.

[0255]FIG. 74 shows a symbol for the 16-Mbit flash memory cores 16MbCOREshown in FIGS. 73A to 73D.

[0256]FIG. 75 is a circuit diagram showing an example of theconfiguration of a column redundancy circuit. Two replaceable circuitsare shown in FIG. 75. An auto column redundancy circuit compares all ofthe block addresses with the stored data about all of the columnaddresses. If all of the addresses coincide, the auto column redundancycircuit outputs signal HITCOL. A read column redundancy circuit comparesall of the block addresses with the page addresses (all the bitsexcluding the two low-order bits in four words/page of the embodiment)CA<2:4>. When all the addresses coincide, the read column redundancycircuit outputs signal HITCOL. As 4-bit fuse data R_10_FUSE<0:3>representing I/O to be replaced with the stored data CA_FUSE<0:1> inintra-page column address CA<0:1>, the fuse data in the hit set isselected and sent to a sense amp data multiplexer.

[0257]FIG. 76 shows a sense amplifier and a circuit that latches thesensed data. At the output terminal of a sense amplifier SA1, there isprovided a latch circuit composed of clocked inverters CINV3, CINV4 andan inverter INV5. There are provided 65 units of this latch circuit,including a redundancy circuit. A latch signal LAT is a signal thatoperates with the timing shown in FIG. 90.

[0258]FIG. 77 shows a read and program verify sense amplifier. The readsense amplifier Read S/A is composed of 128 sense amplifiers Sense amp.,16 current converters, and a reference current converter. The verifysense amplifier Verify S/A is composed of 16 sense amplifiers Sense amp.and two current converters.

[0259] A reference cell is shared by the two sense amplifiers. Thereference current converter switches between a read reference cell and averify reference cell. The reference current converter is shared byeight sense amplifiers. This prevents the area from being wasted,although the reference current converter is composed of a flash memorywith a page mode.

[0260] Use of the read and program verify sense amplifier with the aboveconfiguration enables the reference cell to be shared by the read senseamplifier and the program verify sense amplifier and prevents the verifymargin of the main body cells from deteriorating due to variations inthe reference cell.

[0261]FIGS. 78 and 79 each show a circuit that latches the columnredundancy fuse data. The latch circuit shown in FIG. 78 is composed ofclocked inverters CINV5, CINV6 and an inverter INV6. The latch circuitshown in FIG. 79 is composed of clocked inverters CINV7, CINV8 and aninverter INV7. A latch signal FLAT is a signal that operates with thetiming shown in FIG. 90 explained later.

[0262]FIG. 80 shows a circuit that generates a signal R_HITIOi forcausing a multiplexer shown in FIGS. 81 and 82 to replace the I/O dataspecified by signal R_IO_FS<0:3> with signal SAORD when the word forwhich intra-page address R_CA<0:1> coincides with fuse data R_CA_FS<0:1>is outputted. The circuit is composed of an exclusive OR gate EXOR, aninverter INV8, and an AND gate 25. While in the embodiment, only one bitin 4 words/page can be replaced, use of two sets of signal R_CA_FS<0:1>,R_HITIO and SAORD enables two bits on the page to be replaced.

[0263] The multiplexer shown in FIG. 81 is composed of an AND gate AND26. The multiplexer shown in FIG. 82 is composed of an inverter INV9,AND gates AND27 to AND30, n-channel MOS transistors MQ1 to MQ5, and abuffer BAC3.

[0264]FIG. 83 is a circuit diagram showing an example of theconfiguration of a data latch circuit that holds program data. The datalatch circuit includes clocked inverters CINV9, CINV10 and an inverterINV10.

[0265]FIG. 84 is a circuit diagram showing an example of theconfiguration of a sense latch circuit that verifies a program operationor an erase operation. The sense latch circuit includes a senseamplifier SA2, clocked inverters CINV11, CINV12, and an inverter INV11.

[0266]FIG. 85 is a circuit diagram showing an example of theconfiguration of a circuit that performs column redundancy in an autooperation. This circuit is composed of n-channel MOS transistors CQ1 andCQ2, inverter INV12, and an AND gate AND 31.

[0267]FIG. 86 is a circuit diagram showing a circuit which outputs anend signal PEND for designating the end of program when program dataPDATAi and a verify result PSAOi completely coincide with each other.This circuit includes exclusive OR gates PEXOR0 to PEXOR16 and an ANDgate AND32 .

[0268]FIG. 87 is a circuit diagram of a circuit that transfers the datain the target I/O when column redundancy replacement is performed. Thiscircuit is composed of an inverter INV13 and NAND gates NAND1 and NAND2.

[0269]FIG. 88 is a circuit diagram showing an example of theconfiguration of a program load circuit connected to an auto data line.This circuit is composed of a NOR gate NOR1, a level shifter LS23, andan n-channel MOS transistor PQ1. When program data PDATA is “1,” thedata line is put in the floating state. When program data PDATA is “0,”a write voltage VDDP is applied to the data line.

[0270]FIG. 89 is a timing chart showing an operating waveformrepresenting a program operation. The bank including the selectedaddress goes into the program select state, where word line WL and bitline BL are put in the program bias state and program verify state.

[0271]FIG. 90 is a timing chart showing an operating waveformrepresenting a read operation. It is possible to access a bank that isnot in a program operation or an erase operation. When read pageaddresses A2 to A19 are switched, a pulse-like address transition sensesignal ATD is outputted as a result of the transition. The page data issensed by the sense amplifier and four words of data are latched with apulse LAT signal generated from signal ATD. One word specified byintra-page addresses A0, A1 is outputted from an I/O pad. Thereafter,signal ATD is not outputted only by the switching between A0 and A1. Thelatched data is multiplexed and the resulting data is outputted from theI/O pad.

[0272] TABLE 2 lists the voltage values of the internal power supply ineach internal operation. TABLE 2 VDDR VDDH VDDP VSW VBB Read 5 V  5 VVcc   5 V   0 V Program 5 V 10 V 5 V  10 V   0 V Program 5 V 10 V Vcc6.5 V   0 V verify Erase 5 V 10 V Vcc 2.5 V −7.5 V Erase 5 V 10 V Vcc3.5 V   2 V Verify

[0273] Read word line voltage VDDR keeps the same level in any operatingstate. VDDH, which is at 10 V in any mode other than the read mode,generates VSW for a select word line level. VDDP generates 5 V only in aprogram operation. VBB generates not only a word line level in an eraseoperation but also −2 V in an erase verify operation.

[0274] TABLE 3 lists the bias relationship between theselected/unselected word lines and the bit lines in the selected blockin each operating state and the bias relationship between theselected/unselected word lines and the bit lines in the unselectedblocks. TABLE 3 Selected Unselected Unselected block WL BL Well WL BL WLBL Well Read VDDR 1 V 0 V 0 V floating 0 V floating 0 V Program VSW VDDP0 V 0 V floating 0 V floating 0 V Program VSW 1 V 0 V 0 V floating 0 Vfloating 0 V verify Erase VBB floating VDDH — — 0 V floating 0 V EraseVSW 1 V 0 V 0 V floating 0 V floating 0 V Verify

[0275] Next, address allocation in a nonvolatile semiconductor memorywith the configuration as shown in FIGS. 4 to 90 will be explained.

[0276]FIGS. 91A, 91B, 92A, 92B, 92C, 93A, 93B, 94A, 94B, 94C, 95A, 95B,96A, 96B, 96C, 97A, 97B, 98A, 98B, and 98C show a first to an eighthexample of address allocation in a nonvolatile semiconductor memoryaccording to embodiments of the present invention.

[0277] In the examples of allocation of addresses, addresses A1 to A16are in the ascending order. Thus, address A0 is the lowers, address A1is higher than address A0, address A2 is higher than address A1, and soon, and address A16 is the highest. Four or five address subsets areallocated to each of address A1 to A16. If four address subsets areallocated to each address, the first subset corresponds to theintra-page (column) address, the second subset to the row address, thethird subset to the page (column) address, and the fourth address subsetto the block address. If five address subsets are allocated to eachaddress, the first subset corresponds to the intra-page (column)address, the second subset to the lower row address, the third subset tothe page (column) address, the fourth subset to the upper row address orthe upper row and boot block address, and the fifth subset to the blockaddress.

[0278] The first to eighth examples of address allocation will bedescribed below.

[0279] The first example of address allocation shown in FIGS. 91A and91B is based on the assumption that the configuration includes four512-Kbit (512×1024) blocks. Each block is divided by bit lines BL (4n)to BL(4n+3) into four groups (32 words) in units of 8 words. Each ofpage0 to page4095 is composed of 8 words.

[0280] As shown in FIG. 91A, word line WL0 selects pages page0,paqe1024, page2048, and page3069 and word line WL1 selects pages page1,page1025, page2049, and page3070. Moreover, word line WL2 selects pagespage2, page1026, page2050, and page3071. Similarly, word lines WL3 toWL1022 select pages in the same manner. Then, word line WL1023 selectspages page1023, page2047, page3068, and page4095.

[0281] On the other hand, bit line BL(4n) selects pages page0, page1,page2, . . . , page1023 and bit line BL(4n+1) selects pages page1024,page1025, page1026, . . . , page2047. Furthermore, bit line BL(4n+2)selects pages page2048, page2049, page2050, . . . , page3068 and bitline BL(4n+3) selects pages page3069, page3070, page3071, . . . ,page4095.

[0282] Then, as shown in FIG. 91B, intra-page (column) addresses CA0,CA1, CA2 are allocated to low-order addresses A0, A1, A2; row addressesRA0 to RA9 are allocated to addresses A3 to A12; page (column) addressesCA3, CA4 are allocated to addresses A13, A14; and block addresses BA0,BA1 are allocated to high-order addresses A15, A16.

[0283] With this allocation, one of the four 512-Kbit (512×1024) blocksis selected by block addresses BA0, BA1. Then, one of the four group isselected by page (column) addresses CA3, CA4 and one of word lines WL0to WL1023 is selected by row addresses RA9 to RA9, thereby selecting onepage. Eight words on the selected page are selected by intra-page(column) addresses CA0, CA1, CA2.

[0284] The second example of address allocation shown in FIGS. 92A, 92B,and 92C shows a case where there is a boot block. This example is alsobased on the assumption that the configuration includes four 512-Kbit(512×1024) blocks. Each block is divided by bit lines BL(4n) to BL(4n+3)into four groups (32 words) in units of 8 words. Each of page0 topage4095 is composed of 8 words.

[0285] As shown in FIG. 92A, the size of the configuration is ⅛ of thesize of the configuration of FIG. 91A. Word line WL0 selects pagespage0, page128, page256, page 384 and word line WL1 selects pages page1,page129, page257, page385. Moreover, word line WL2 selects pages page2,page130, page258, page386. Similarly, word lines WL3 to WL126 selectpages in the same manner. Then, word line WL127 selects pages page127,page255, page383, page511.

[0286] Furthermore, bit line BL(4n) selects pages page0, page1, page2, .. . , page127 and bit line BL(4n+1) selects pages page128, page129,page130, . . . , page255. Moreover, bit line BL(4n+2) selects pagespage256, page257, page258, . . . , page383 and bit line BL(4n+3) selectspages page384, page385, page386, . . . , page511.

[0287] Then, as shown in FIG. 92B, intra-page (column) addresses CA0,CA1, CA2 are allocated to low-order addresses A0, A1, A2; lower rowaddresses RA0 to RA6 are allocated to addresses A3 to A9; page (column)addresses CA3, CA4 are allocated to addresses A10, A11; upper rowaddresses & boot block addresses RA7, RA8, RA9 are allocated toaddresses A12, A13, A14; and block addresses BA0, BA1 are allocated tohigh-order addresses A15, A16.

[0288] In this case, page (column) addresses CA3, CA4 select one of thefour groups and row addresses RA0 to RA6 select one of word lines WL0 toWL127, thereby selecting one page. Eight words in the selected page areselected by intra-page (column) addresses CA0, CA1, CA2.

[0289]FIG. 92C shows a combination of eight units of the configurationshown in FIG. 92A. As shown in FIG. 92B, one of the four 512-Kbit blocksis selected by block addresses BA0 and BA1. One of the eight units isselected by row addresses RA7, RA8 and RA9.

[0290] The third example of address allocation shown in FIGS. 93A and93B is based on the assumption that the configuration includes four512-Kbit (512×1024) blocks. Each block is divided by bit lines BL(8n) toBL(8n+7) into eight groups (32 words) in units of 4 words. Each of page0to page8191 is composed of 4 words.

[0291] As shown in FIG. 93A, word line WL0 selects pages page0,page1024, . . . , page7168 and word line WL1 selects pages page1,page1025, . . . , page7169. Moreover, word line WL2 selects pages page2,page1026, . . . , page7170. Similarly, word lines WL3 to WL1022 selectpages in the same manner. Then, word line WL1023 selects pages page1023,page2047, . . . , page8191.

[0292] On the other hand, bit line BL(8n) selects pages page0, page1,page2, . . . , page1023 and bit line BL(8n+1) selects pages page1024,page1025, page1026, page2047. Similarly, bit lines BL(8n+2) to BL(8n+6)select pages in the same manner. Then, bit line BL(8n+7) selects pagespage7168, page7169, page7170, . . . , page8191.

[0293] Then, as shown in FIG. 93B, intra-page (column) addresses CA0,CA1 are allocated to low-order addresses A0, A1; row addresses RA0 toRA9 are allocated to addresses A2 to A11; page (column) addresses CA2,CA3, CA4 are allocated to addresses A12, A13, A14; and block addressesBA0, BA1 are allocated to high-order addresses A15, A16.

[0294] With this allocation, block addresses BA0, BA1 select one of thefour 512-Kbit (512×1024) blocks. In addition, page (column) addressesCA2, CA3, CA4 select two of the eight groups and row addresses RA0 toRA9 select one of word lines WL0 to WL1023, thereby selecting twoconsecutive pages. Eight words on the selected two pages are selected byintra-page (column) addresses CA0, CA1 and CA2.

[0295] The fourth example of address allocation shown in FIGS. 94A, 94Band 94C shows a case where there is a boot block. This example is alsobased on the assumption that the configuration includes four 512-Kbit(512×1024) blocks. Each block is divided by bit lines BL(8n) to BL(8n+7)into eight groups (32 words) in units of 4 words. Each of page0 topage8191 is composed of 4 words.

[0296] As shown in FIG. 94A, the size of the configuration is ⅛ of thesize of the configuration of FIG. 93A. Word line WL0 selects pagespage0, page128, . . . , page 896 and word line WL1 selects pages page1,page129, . . . , page897. Moreover, word line WL2 selects pages page2,page130, . . . , page898. Similarly, word lines WL3 to WL126 selectpages in the same manner. Then, word line WL127 selects pages page127,page255, . . . , page1023.

[0297] Furthermore, bit line BL(8n) selects pages page0, page1, page2, .. . , page127 and bit line BL(8n+1) selects pages page128, page129,page130, . . . , page255. Similarly, bit lines BL(8n+2) to BL(8n+6)select pages in the same manner. Then, bit line BL(8n+7) selects pagespage896, page897, page898, . . . , page1023.

[0298] Then, as shown in FIG. 94B, intra-page (column) addresses CA0,CA1 are allocated to low-order addresses A0, A1; lower row addresses RA0to RA6 are allocated to addresses A2 to A8; page (column) addresses CA2,CA3, CA4 are allocated to addresses A9, A10, A11; upper row addresses &boot block addresses RA7, RA8, RA9 are allocated to addresses A12, A13,A14; and block addresses BA0, BA1 are allocated to high-order addressesA15, A16.

[0299] In this case, page (column) addresses CA2, CA3, CA4 select two ofthe eight groups and lower row addresses RA0 to RA6 select one of wordlines WL0 to WL127, thereby selecting two consecutive pages. Eight wordson the selected two pages are selected by intra-page (column) addressesCA0, CA1.

[0300]FIG. 94C shows a combination of eight units of the configurationshown in FIG. 94A. As shown in FIG. 94B, one of the four 512-Kbit(512×1024) blocks is selected by block addresses BA0, BA1. One of theeight units is selected by upper row addresses & boot block addressesRA7, RA8 and RA9.

[0301] The fifth example of address allocation shown in FIGS. 95A and95B is based on the assumption that the configuration includes four512-Kbit (1024×512) blocks. Each block is divided by bit lines BL(8n) toBL(8n+7) into eight groups (64 words) in units of 8 words. Each of page0to page4095 is composed of 8 words.

[0302] As shown in FIG. 95A, word line WL0 selects pages page0, page512,. . . , page3584 and word line WL1 selects pages page1, page513, . . . ,page3585. Moreover, word line WL2 selects pages page2, page514, . . . ,page3586. Similarly, word lines WL3 to WL510 select pages in the samemanner. Then, word line WL511 selects pages page511, page1023, . . . ,page4095.

[0303] On the other hand, bit line BL(8n) selects pages page0, page1,page2, . . . , page511 and bit line BL(8n+1) selects pages page512,page513, page514, . . . , page1023. Similarly, bit lines BL(8n+2) toBL(8n+6) select pages in the same manner. Then, bit line BL(8n+7)selects pages page3584, page3585, page3586, . . . , page4095.

[0304] Then, as shown in FIG. 95B, intra-page (column) addresses CA0,CA1 are allocated to low-order addresses A0, A1; row addresses RA0 toRA8 are allocated to addresses A2 to A10; page (column) addresses CA2,CA3, CA4, CA5 are allocated to addresses A11, A12, A13, A14; and blockaddresses BA0, BA1 are allocated to high-order addresses A15, A16.

[0305] With this allocation, block addresses BA0 and BA1 select one ofthe four 512-Kbit (1024×512) blocks. In addition, page (column)addresses CA2, CA3, CA4 and CA5 select one of the eight groups and rowaddresses RA0 to RA8 select one of word lines WL0 to WL511, therebyselecting one page. Eight words on the selected page are selected byintra-page (column) addresses CA0, CA1.

[0306] The sixth example of address allocation shown in FIGS. 96A, 96Band 96C shows a case where there is a boot block. This example is alsobased on the assumption that the configuration includes four 512-Kbit(1024×512) blocks. Each block is divided by bit lines BL(8n) to BL(8n+7)into eight groups (64 words) in units of 8 words. Each of page0 topage4095 is composed of 8 words.

[0307] As shown in FIG. 96A, the size of the configuration is ⅛ of thesize of the configuration of FIG. 95A. Word line WL0 selects pagespage0, page64, . . . , page448 and word line WL1 selects pages page1,page65, . . . , page449. Moreover, word line WL2 selects pages page2,page66, . . . , page450. Similarly, word lines WL3 to WL62 select pagesin the same manner. Then, word line WL63 selects pages page63, page127,. . . , page511.

[0308] Furthermore, bit line BL(8n) selects pages page0, page1, page2, .. . , page63 and bit line BL(8n+1) selects pages page64, page65, page66,. . . , page127. Similarly, bit lines BL(8n+2) to BL(8n+6) select pagesin the same manner. Then, bit line BL(8n+7) selects pages page448,page459, page450, . . . , page511.

[0309] Then, as shown in FIG. 96B, intra-page (column) addresses CA0,CA1 are allocated to low-order addresses A0, A1 (first address subset);row addresses RA0 to RA6 are allocated to addresses A2 to A8 (secondaddress subset); page (column) addresses CA2, CA3, CA4 are allocated toaddresses A9, A10, A11 (third address subset); upper row addresses &boot block addresses RA7, RA8, RA9 are allocated to addresses A12, A13,A14 (forth address subset); and block addresses BA0, BA1 are allocatedto high-order addresses A15, A16 (fifth address subset).

[0310] In this case, page (column) addresses CA2, CA3 and CA4 select oneof the eight groups and row addresses RA0 to RA6 select one of wordlines WL0 to WL511, thereby selecting one page. Eight words on theselected page are selected by intra-page (column) addresses CA0, CA1.

[0311]FIG. 96C shows a combination of eight units, each identical to theconfiguration shown in FIG. 96A. As FIG. 96B depicts, one of the four512-Kbit (512×1024) blocks is selected by block addresses BA0 and BA1.One of the eight units is selected by row addresses RA7, RA8 and RA9.

[0312]FIGS. 96D to 96F show structural examples of the address buffer 23(see FIG. 4), which is used for realizing the examples of the sixthaddress allocation shown in FIGS. 96A, 96B and 96C. FIG. 96D is acircuit diagram illustrating an i-th bit buffer circuit incorporated inthe address buffer 23. FIG. 96E is a symbolic view of the buffer circuitshown in FIG. 96D. FIG. 96F is a block diagram illustrating structuralexamples of the address buffer of FIG. 4.

[0313] As seen from FIG. 96D, each bit of the address buffer 23 isprovided with a buffer circuit that comprises a NOR gate NOR2, invertersINV14, INV15 and INV16, and clocked inverter CINV13. One input terminalof the NOR gate NOR2 is supplied with a chip enable signal CEB. The chipenable signal CEB is supplied from the controller 21, and is low-levelupon selection of a chip. The other input terminal of the NOR gate NOR2is connected to the i-th bit input pad ADDPADi for the address signalADD. The output terminal of the NOR gate NOR2 is connected to the inputterminal of the inverter INV14. The output terminal of the inverterINV14 outputs a signal R_Ai, and is connected to the input terminal ofthe clocked inverter CINV13. The clock input terminal of the clockedinverter CINV13 is controlled by an enable signal ADDINEN supplied fromthe controller 21 for address input for automatic writing and erasure.The output terminal of the clocked inverter CINV13 is connected to theinput terminal of the inverter INV15. The output and input terminals ofthe inverter INV15 are connected to the input and output terminals ofthe inverter INV16, respectively. As a result, the inverters INV15 andINV16 provide a latch circuit. The output terminal of the INV15 outputsa signal A_Ai.

[0314] The buffer circuit is constructed under the presumption of dualoperation, and the signal ADDINEN is a control signal for fetching anaddress for writing and erasure into the decoder.

[0315] If the buffer circuit shown in FIG. 96D is expressed by a symbolfigure (ADDBUF) as shown in FIG. 96E, the address buffer 23 shown inFIG. 4 is expressed as shown in FIG. 96F. A buffer circuit ADDBUF1corresponds to the first address subset, and outputs signalsR_CAj(j=0−1) and A_CAj(j=0−1) on the basis of 0-th and 1-st bit addresssignals ADDi input to the chip enable signal CEB and address pad ADDPADi(i=0−1), respectively. The signal ADDINEN is a control signal forfetching the intra-page (column) address into the column decoder 13 forwriting and erasure. A buffer circuit ADDBUF2 corresponds to the secondaddress subset, and outputs signals R_CAj(j=0−6) and A_CAj(j=0−6) on thebasis of 2-nd to 8-th bit address signals ADDi input to the chip enablesignal CEB and address pad ADDPADi (i=2−8), respectively. The signalADDINEN is a control signal for fetching the lower row address into therow decoder 12 for writing and erasure. A buffer circuit ADDBUF3corresponds to the third address subset, and outputs signalsR_CAj(j=2−4) and A CAj(j=2−4) on the basis of 9-th to 1-th bit addresssignals ADDi input to the chip enable signal CEB and address pad ADDPADi(i=9−11), respectively. The signal ADDINEN is a control signal forfetching the page (column) address into the column decoder 13 forwriting and erasure. A buffer circuit ADDBUF4 corresponds to the fourthaddress subset, and outputs signals R_CAj(j=7−9) and A_CAj(j=7−9) on thebasis of 12-th to 14-th bit address signals ADDi input to the chipenable signal CEB and address pad ADDPADi (i=12−14), respectively. Thesignal ADDINEN is a control signal for fetching the upper row and bootblock addresses into the row decoder 12 for writing and erasure. Abuffer circuit ADDBUF5 corresponds to the fifth address subset, andoutputs signals R_CAj(j=1−2) and A CAj(j=1−2) on the basis of 15-th and16-th bit address signals ADDi input to the chip enable signal CEB andaddress pad ADDPADi (i=15−16), respectively. The signal ADDINEN is acontrol signal for fetching the block address into the block decoder 14for writing and erasure.

[0316] The seventh example of address allocation shown in FIGS. 97A and97B is based on the assumption that the configuration includes four512-Kbit (1024×512) blocks. Each block is divided by bit lines BL(16n)to BL(16n+15) into 16 groups (64 words) in units of 4 words. Each ofpage0 to page8191 is composed of 4 words.

[0317] As shown in FIG. 97A, word line WL0 selects pages page0, page512,. . . , page7680 and word line WL1 selects pages page1, page513, . . . ,page7681. Moreover, word line WL2 selects pages page2, page514, . . . ,page7682. Similarly, word lines WL3 to WL510 select pages in the samemanner. Then, word line WL511 selects pages page511, page1023, . . . ,page8191.

[0318] On the other hand, bit line BL(16n) selects pages page0, page1,page2, . . . , page511 and bit line BL(16n+1) selects pages page512,page513, page514, . . . , page1023. Similarly, bit lines BL(16n+2) toBL(16n+14) select pages in the same manner. Then, bit line BL(16n+15)selects pages page7680, page7681, page7682, page8191.

[0319] Then, as shown in FIG. 97B, intra-page (column) addresses CA0,CA1 are allocated to low-order addresses A0, A1; row addresses RA0 toRA8 are allocated to addresses A2 to A10; page (column) addresses CA2 toCA5 are allocated to addresses A11 to A14; and block addresses BA0, BA1are allocated to high-order addresses A15, A16.

[0320] With this allocation, block addresses BA0, BA1 select one of thefour 512-Kbit (1024×512) blocks. In addition, page (column) addressesCA2 to CA5 select one of the 16 groups and row addresses RA0 to RA8select one of word lines WL0 to WL511, thereby selecting one page. Fourwords on the selected page are selected by intra-page (column) addressesCA0, CA1.

[0321] The eighth example of address allocation shown in FIGS. 98A, 98B,and 98C shows a case where there is a boot block. This example is alsobased on the assumption that the configuration includes four 512-Kbit(1024×512) blocks. Each block is divided by bit lines BL(16n) toBL(16n+15) into 16 groups (64 words) in units of 4 words. Each of page0to page8191 is composed of 4 words.

[0322] As shown in FIG. 98A, the size of the configuration is ⅛ of thesize of the configuration of FIG. 97A. Word line WL0 selects pagespage0, page64, . . . , page960 and word line WL1 selects pages page1,page65, . . . , page961. Moreover, word line WL2 selects pages page2,page66, . . . , page962. Similarly, word lines WL3 to WL62 select pagesin the same manner. Then, word line WL63 selects pages page63, page127,. . . , page1023.

[0323] Furthermore, bit line BL(16n) selects pages page0, page1, page2,. . . , page63 and bit line BL(16n+1) selects pages page64, page65,page66, . . . , page127. Similarly, bit lines BL(16n+2) to BL(16n+14)select pages in the same manner. Then, bit line BL(16n+15) selects pagespage960, page961, page962, . . . , page1023.

[0324] Then, as shown in FIG. 98B, intra-page (column) addresses CA0,CA1 are allocated to low-order addresses A0, A1; lower row addresses RA0to RA5 are allocated to addresses A2 to A7; page (column) addresses CA2to CA5 are allocated to addresses A8 to A11; upper row addresses & bootblock addresses RA6, RA7, RA8 are allocated to addresses A12, A13, A14;and block addresses BA0, BA1 are allocated to high-order addresses A15,A16.

[0325] In this case, page (column) addresses CA2 to CA5 select one ofthe 16 groups and row addresses RA0 to RA5 select one of word lines WL0to WL511, thereby selecting one page. Four words on the selected pageare selected by intra-page (column) addresses CA0 and CA1.

[0326]FIG. 98C shows a combination of 16 units of the configurationshown in FIG. 98A. As shown in FIG. 98B, one of the four 512-Kbit(1024×512) blocks is selected by block addresses BA0 and BA1. One of the16 units is selected by row addresses RA7, RA8 and RA9.

[0327] As described above, in the examples shown in FIGS. 91A and 91B,93A and 93B, 95A and 95B, 97A and 97B intra-page (column) addresses areallocated to low-order addresses, row addresses are allocated tomiddle-order addresses, page (column) addresses are allocated toaddresses higher in order than the middle-order addresses, and blockaddresses are allocated to the highest-order addresses.

[0328] In the examples shown in FIGS. 92A to 92C, 94A to 94C; 96A to96C, and 98A to 98C, intra-page (column) addresses are allocated tolow-order addresses, low-order row addresses are allocated tomiddle-order addresses, page (column) addresses are allocated toaddresses higher in order than the middle-order addresses, high-orderrow addresses are allocated to addresses higher in order than the page(column) addresses, and block addresses are allocated to thehighest-order addresses.

[0329] The latter is effective in the case of a flash memory including8-Kbyte boot blocks.

[0330] In the above-described allocation examples of the first to eighthaddresses, four or five address subsets are allocated. However, the sameadvantageous effect can be obtained even if three address subsets areallocated. In this case, the column address is allocated to the firstaddress subset, the row address is allocated to the second addresssubset, and the second column address is allocated to the third addresssubset. This address allocation provides the same advantageous effect asthat obtained in the above-described allocation examples of the first toeighth addresses.

[0331] Next, the read disturb time is calculated in the alreadydescribed example (the case where cells for 32 words are connected to asingle word line and 128 consecutive words continue to be read for 10years). When the page size is 8 words (for example, see FIGS. 91A and91B), 128 words are distributed to 16 word lines. Since 8 words can beread in the read time required to read one word, the word line stresstime for the time required to read 8 words is ⅛. Moreover, the number ofword lines decreases to {fraction (16/128)}, the length of time that oneword line is selected becomes 8 times the present value. As a result,the word line stress time (or read disturb time) can be made identicalwith that when no page mode function is used. Of course, the same holdstrue for other examples, in addition to the examples of FIGS. 91A and91B.

[0332] Therefore, it is possible to provide a nonvolatile semiconductormemory capable of suppressing an increase in the read disturb time ofthe nonvolatile semiconductor memory with a page mode (page readingfunction) to a conventional level and assuring the same reliability asthat of a conventional equivalent.

[0333] As described above, according to an aspect of the presentinvention, there is provided a nonvolatile semiconductor memory capableof, although having a page mode, making the read disturb time equivalentto that of a nonvolatile semiconductor memory without a page mode.

[0334] Additional advantages and modifications will readily occur tothose skilled in the art. Therefore, the invention in its broaderaspects is not limited to the specific details and representativeembodiments shown and described herein. Accordingly, variousmodifications may be made without departing from the spirit or scope ofthe general inventive concept as defined by the appended claims andtheir equivalents.

1-4. (Canceled).
 5. A nonvolatile semiconductor memory with at least asmany sense amplifiers as correspond to ₂N1 words comprising: a pluralityof nonvolatile memory cells; a plurality of word lines and a pluralityof bit lines which are connected to said plurality of nonvolatile memorycells; an address buffer to which an N1 number of address subset of thelowest order are inputted as a first column address, an N2 number ofaddress subset higher than any of said N1 number of address subset areinputted as a first row address, and an N3 number of address subsethigher in order than any of said N2 number of address subset areinputted as a second column address; and a decoder to which the outputsignal of said address buffer is supplied and which is configured toselect at least one of said plurality of nonvolatile memory cells,wherein said plurality of bit lines are selected by at least said secondcolumn address, and said plurality of word lines are selected by atleast said first row address.
 6. The nonvolatile semiconductor memoryaccording to claim 5, wherein said address buffer further takes in an N4number of address subset higher in order than any of said N3 number ofaddress subset as second row address.
 7. The nonvolatile semiconductormemory according to claim 6, wherein said plurality of nonvolatilememory cells are arranged in a matrix to form a memory cell array, saidmemory cell array divided into a plurality of blocks, each of saidplurality of blocks is selected by a block address, and said addressbuffer further takes in an N5 number of address subset higher in orderthan any of said N4 number of address subset as the block address. 8.The nonvolatile semiconductor memory according to claim 5, wherein saidplurality of nonvolatile memory cells are arranged in a matrix to form amemory cell array, said memory cell array divided into a plurality ofblocks, each of said plurality of blocks is selected to a block address,and said address buffer further takes in an N5 number of address subsethigher in order than any of said N3 number of address subset as theblock address. 9-16 (Canceled)